24 lines
471 B
Systemverilog
24 lines
471 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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task foo;
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#1 if ($time != 1) $stop;
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#1 if ($time != 2) $stop;
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#1 if ($time != 3) $stop;
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endtask
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initial fork
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foo;
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foo;
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foo;
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#4 begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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join
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endmodule
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