2022-10-22 19:45:48 +02:00
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%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:11: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r'
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2023-09-23 14:52:50 +02:00
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: ... note: In instance 't'
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2022-10-22 19:45:48 +02:00
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14 | assign r = 1'b0;
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... For error description see https://verilator.org/warn/CONTASSREG?v=latest
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%Error: Exiting due to
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