2017-12-14 01:49:37 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 16:24:24 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2017-12-14 01:49:37 +01:00
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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always_comb @(*) begin
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$stop;
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end
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endmodule
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