2019-11-05 03:51:20 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 16:24:24 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2019-11-05 03:51:20 +01:00
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//bug1587
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module t;
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reg a[0];
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reg b;
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reg c;
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initial c = (a != &b);
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endmodule
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