75 lines
1.2 KiB
Systemverilog
75 lines
1.2 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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static int x = 1;
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endclass
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class Bar;
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Foo f;
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function new;
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f = new;
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endfunction
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endclass
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class Baz;
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function static Bar get_bar;
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Bar b = new;
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return b;
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endfunction
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endclass
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class IntWrapper;
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int x;
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endclass
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class Cls;
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static IntWrapper iw;
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function new;
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if (iw == null) iw = new;
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endfunction
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endclass
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class ExtendCls extends Cls;
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endclass
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class Getter1;
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function static int get_1;
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return 1;
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endfunction
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endclass
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module t (/*AUTOARG*/
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);
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initial begin
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Foo foo = new;
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Bar bar = new;
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Baz baz = new;
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ExtendCls ec = new;
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Getter1 getter1 = new;
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if (foo.x != 1) $stop;
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foo.x = 2;
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if (foo.x != 2) $stop;
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bar.f.x = 3;
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if (bar.f.x != 3) $stop;
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baz.get_bar().f.x = 4;
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if (baz.get_bar().f.x != 4) $stop;
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ec.iw.x = 5;
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if (ec.iw.x != 5) $stop;
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if (getter1.get_1 != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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