13 lines
238 B
Systemverilog
13 lines
238 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t
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(
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input wire i,
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input wire i2 = i // BAD
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);
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endmodule
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