verilator/test_regress/t/t_interface_top_bad.out

%Error: t/t_interface_top_bad.v:16:19: Unsupported: Interfaced port on top level module
   ifc.counter_mp c_data
                  ^~~~~~
%Error: t/t_interface_top_bad.v:16:4: Parent cell's interface is not found: 'ifc'
   ifc.counter_mp c_data
   ^~~
%Error: Exiting due to
Add column numbers to errors and warnings. 2020-03-15 03:02:42 +01:00			`%Error: t/t_interface_top_bad.v:16:19: Unsupported: Interfaced port on top level module`
When showing an error, show source code. 2019-07-15 03:42:03 +02:00			`ifc.counter_mp c_data`
			`^~~~~~`
Add column numbers to errors and warnings. 2020-03-15 03:02:42 +01:00			`%Error: t/t_interface_top_bad.v:16:4: Parent cell's interface is not found: 'ifc'`
When showing an error, show source code. 2019-07-15 03:42:03 +02:00			`ifc.counter_mp c_data`
			`^~~`
Tests: Add additional .out files instead of expects. 2019-06-13 03:49:40 +02:00			`%Error: Exiting due to`