1911 lines
92 KiB
Plaintext
1911 lines
92 KiB
Plaintext
|
// Generated by verilated_saif
|
||
|
|
(SAIFILE
|
||
|
|
(SAIFVERSION "2.0")
|
||
|
|
(DIRECTION "backward")
|
||
|
|
(PROGRAM_NAME "Verilator")
|
||
|
|
(DIVIDER / )
|
||
|
|
(TIMESCALE 1ps)
|
||
|
|
(DURATION 170)
|
||
|
|
(INSTANCE top
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
)
|
||
|
|
(INSTANCE t
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(out0\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out0\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out0\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out0\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out0\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out1\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out1\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out1\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out1\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out1\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out3\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out3\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out3\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out3\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out3\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out3_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out3_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out3_2\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out3_2\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out3_2\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out5\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out5\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out5\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out5\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out5\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out6\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out6\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(out6\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out6\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(out6\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_delay0
|
||
|
|
(NET
|
||
|
|
(N\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(tmp\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(tmp\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(tmp\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(tmp\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE genblk1
|
||
|
|
(INSTANCE i_delay
|
||
|
|
(NET
|
||
|
|
(N\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(tmp\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(tmp\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(tmp\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_delay1
|
||
|
|
(NET
|
||
|
|
(N\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(N\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(out\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(out\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(tmp\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 9))
|
||
|
|
(tmp\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(tmp\[4\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE genblk1
|
||
|
|
(INSTANCE i_delay
|
||
|
|
(NET
|
||
|
|
(N\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 9))
|
||
|
|
(in\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(in\[4\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(out\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(out\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(tmp\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 9))
|
||
|
|
(tmp\[2\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(tmp\[4\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE genblk1
|
||
|
|
(INSTANCE i_delay
|
||
|
|
(NET
|
||
|
|
(N\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 9))
|
||
|
|
(in\[2\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(in\[4\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(out\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(out\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(tmp\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(tmp\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(tmp\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||
|
|
(tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(tmp\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(in\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(ff\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(ff\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out4\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out4\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out4_2\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out4_2\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4_2\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_0
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_1
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3_2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(in\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(ff\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(ff\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out4\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out4\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out4_2\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out4_2\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4_2\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_0
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_1
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE top.t.i_sub0.i_sub0
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE sub0
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE top.t.i_sub1
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE sub1
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(out\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(ff\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(ff\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE top.t.i_sub2
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE sub2
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE in_ifs
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(data\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(data\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE out_ifs
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(data\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(data\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(in_wire\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in_wire\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in_wire\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in_wire\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in_wire\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out_1\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out_1\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out_1\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out_1\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out_1\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out_2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out_2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out_2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE in
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(data\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(data\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE out
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(data\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(data\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(ff\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out4\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out4_2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4_2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4_2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_0
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_1
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3_2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||
|
|
(in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(ff\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out4\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out4_2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out4_2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out4_2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_0
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub4_1
|
||
|
|
(NET
|
||
|
|
(P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||
|
|
(ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||
|
|
(ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||
|
|
(ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE top.t.i_sub3.i_sub4_0.i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
(INSTANCE sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE top.t.i_sub3.i_sub4_1.i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
(INSTANCE sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE top.t.i_sub3_2.i_sub4_0.i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
(INSTANCE sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE top.t.i_sub3_2.i_sub4_1.i_sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
(INSTANCE sub5
|
||
|
|
(NET
|
||
|
|
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||
|
|
(in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||
|
|
(count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||
|
|
(count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||
|
|
(count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||
|
|
(count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub0
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub1
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub2
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE i_sub3
|
||
|
|
(NET
|
||
|
|
(P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk1
|
||
|
|
(NET
|
||
|
|
(i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk2
|
||
|
|
(NET
|
||
|
|
(j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
(j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||
|
|
)
|
||
|
|
(INSTANCE unnamedblk3
|
||
|
|
(NET
|
||
|
|
(exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
(exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|