33 lines
670 B
Systemverilog
33 lines
670 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Alias type check error test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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interface Bus;
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bit data;
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endinterface
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module t;
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Bus intf();
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virtual Bus vif = intf;
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bit ok = 0;
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function logic write_data(output bit data);
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data = ~data;
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return data;
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endfunction
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initial @(posedge vif.data) ok = 1;
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initial begin
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#1;
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while (!write_data(vif.data)) $stop;
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#1 if (ok != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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