2019-06-05 02:37:16 +02:00
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// DESCRIPTION: Verilator: Large test for SystemVerilog
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012.
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2019-06-05 02:37:16 +02:00
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// Contributed by M W Lund, Atmel Corporation.
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// **** Set simulation time scale ****
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`timescale 1ns/1ps
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