55 lines
1.2 KiB
Systemverilog
55 lines
1.2 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class One #(
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type VALUE_T = int unsigned
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);
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typedef One#(VALUE_T) self_t;
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VALUE_T value;
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extern static function self_t create(VALUE_T value);
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endclass
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class Two #(
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type VALUE_T = int unsigned
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);
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VALUE_T value;
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extern static function Two#(VALUE_T) create(VALUE_T value);
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`ifdef NEVER
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// works ok if put function directly here
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static function Two#(VALUE_T) create(VALUE_T value);
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Two #(VALUE_T) obj = new();
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obj.value = value;
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return obj;
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endfunction
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`endif
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endclass
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function One::self_t One::create(VALUE_T value);
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One #(VALUE_T) obj = new();
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obj.value = value;
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return obj;
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endfunction
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function Two#(Two::VALUE_T) Two::create(VALUE_T value);
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Two #(VALUE_T) obj = new();
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obj.value = value;
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return obj;
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endfunction
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module t;
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initial begin
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One #(string) one;
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Two #(string) two;
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one = One#(string)::create("one");
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two = Two#(string)::create("two");
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if (one.value !== "one") $stop;
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if (two.value !== "two") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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