55 lines
1.6 KiB
Systemverilog
55 lines
1.6 KiB
Systemverilog
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// DESCRIPTION: Verilator: Test transition bins - restart behavior
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// Known limitation: multi-value transition bins with restart semantics generate
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// incomplete case statements; complex transitions are not fully supported.
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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logic [2:0] state;
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covergroup cg;
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cp_state: coverpoint state {
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bins trans_restart = (1 => 2 => 3); // Should handle restart correctly
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}
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endgroup
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cg cg_inst = new;
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initial begin
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// Sequence: 1, 2, 1, 2, 3
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// This tests restart logic: when we see 1 again while in middle of sequence,
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// we should restart from position 1 (not reset to 0)
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state = 1; // Start: position = 1
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cg_inst.sample();
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`checkr(cg_inst.get_inst_coverage(), 0.0);
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state = 2; // Advance: position = 2
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cg_inst.sample();
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`checkr(cg_inst.get_inst_coverage(), 0.0);
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state = 1; // Restart! Should go to position 1 (not 0)
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cg_inst.sample();
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`checkr(cg_inst.get_inst_coverage(), 0.0);
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state = 2; // Advance: position = 2
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cg_inst.sample();
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`checkr(cg_inst.get_inst_coverage(), 0.0);
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state = 3; // Complete! Bin should increment
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cg_inst.sample();
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`checkr(cg_inst.get_inst_coverage(), 100.0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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