50 lines
1.3 KiB
Systemverilog
50 lines
1.3 KiB
Systemverilog
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// DESCRIPTION: Verilator: Assignment pattern preserves array expression side effects
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-FileCopyrightText: 2026 Rowan Goemans
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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// verilator lint_off ASCRANGE
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typedef logic [0:2][7:0] triple_lv_t;
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// verilator lint_on ASCRANGE
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typedef triple_lv_t pair_t [0:1];
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function automatic triple_lv_t mk3(
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input logic [7:0] a,
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input logic [7:0] b,
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input logic [7:0] c
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);
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mk3 = '{0: a, 1: b, 2: c};
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endfunction
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pair_t pair;
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initial begin
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// verilator lint_off SIDEEFFECT
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pair = '{
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0: mk3(8'd1, 8'd2, 8'd3),
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1: mk3(8'd4, 8'd5, 8'd6)
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};
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// verilator lint_on SIDEEFFECT
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`checkd(pair[0][0], 8'd1);
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`checkd(pair[0][1], 8'd2);
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`checkd(pair[0][2], 8'd3);
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`checkd(pair[1][0], 8'd4);
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`checkd(pair[1][1], 8'd5);
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`checkd(pair[1][2], 8'd6);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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