71 lines
1.8 KiB
Systemverilog
71 lines
1.8 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`ifdef verilator
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`define no_optimize(v) $c(v)
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`else
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`define no_optimize(v) (v)
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`endif
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// verilog_format: on
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// verilator lint_off MULTIDRIVEN
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interface ifc;
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// Tristate net resolved across an inout port connected hierarchically to
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// this interface signal (iface.data <-> dut inout port).
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wire [7:0] data;
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endinterface
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module dut (
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inout wire [7:0] data,
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input bit oe,
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input logic [7:0] val
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);
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// The inout port drives the interface net when enabled, releases it (Z) otherwise.
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assign data = oe ? val : 8'hzz;
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endmodule
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module t;
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ifc ifc0 ();
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bit oe, top_oe;
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logic [7:0] val, topval;
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// A second driver from the top, so resolution is observable from both sides.
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assign ifc0.data = top_oe ? topval : 8'hzz;
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dut u (
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.data(ifc0.data),
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.oe(oe),
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.val(val)
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);
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initial begin
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// dut drives the interface net through the inout port.
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oe = `no_optimize(1'b1);
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val = `no_optimize(8'hA5);
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top_oe = `no_optimize(1'b0);
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topval = `no_optimize(8'h00);
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#1;
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`checkh(ifc0.data, 8'hA5);
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// top drives, dut releases.
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oe = `no_optimize(1'b0);
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top_oe = `no_optimize(1'b1);
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topval = `no_optimize(8'h3C);
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#1;
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`checkh(ifc0.data, 8'h3C);
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// Neither drives: net floats to Z.
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oe = `no_optimize(1'b0);
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top_oe = `no_optimize(1'b0);
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#1;
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`checkh(ifc0.data, 8'hzz);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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