32 lines
815 B
Systemverilog
32 lines
815 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int value = 1;
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int other = 2;
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int result;
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bit flag;
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function automatic int passthrough(input int arg);
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return arg;
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endfunction
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initial begin
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result = passthrough({<<{value}});
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result = {<<{value}} + 1;
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result = value + {<<{value}};
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result = value[0] ? {<<{value}} : other;
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result = {{<<{value}}};
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flag = ({<<{value}} == other);
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$display({<<{value}});
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$display("%0d", {<<{value}});
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void'($sformatf("%0d", {<<{value}}));
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result = passthrough({<<{value}} + 1);
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result = int'({<<{value}});
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result = int'({<<{value}}) + 1;
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end
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endmodule
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