25 lines
545 B
Systemverilog
25 lines
545 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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covergroup cg_opt;
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type_option.weight = 1; // ok
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option.name = "the_name"; // pk
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bad_cg_non_option.name = "xx"; // <--- Bad
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endgroup
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covergroup cg_cross3;
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cross a, b{
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option.comment = "cross"; // ok
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bad_cross_non_option.name = "xx"; // <--- Bad
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}
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endgroup
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initial $stop;
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endmodule
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