46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class myClass;
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covergroup embeddedCg;
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cp_mc: coverpoint 1'b1;
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endgroup
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function new();
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real cov_result;
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embeddedCg = new();
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embeddedCg.sample();
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cov_result = embeddedCg.get_coverage();
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if (!(cov_result >= 0.0 && cov_result <= 100.0))
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$error("%m: get_coverage() out of range: %f", cov_result);
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endfunction
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endclass
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class secondClass;
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covergroup embeddedCg;
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cp_sc: coverpoint 1'b0;
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endgroup
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function new();
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real cov_result;
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embeddedCg = new();
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embeddedCg.sample();
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cov_result = embeddedCg.get_coverage();
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if (!(cov_result >= 0.0 && cov_result <= 100.0))
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$error("%m: get_coverage() out of range: %f", cov_result);
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endfunction
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endclass
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module t;
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myClass mc;
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secondClass sc;
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initial begin
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mc = new();
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sc = new();
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$finish;
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end
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endmodule
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