verilator/test_regress/t/t_cover_fsm_sel_assign.out

//      // verilator_coverage annotation
        // DESCRIPTION: Verilator: Verilog Test module
        //
        // This file ONLY is placed under the Creative Commons Public Domain
        // SPDX-FileCopyrightText: 2026 Antmicro
        // SPDX-License-Identifier: CC0-1.0
        
        module t #(
            parameter int unsigned W = 16,
            parameter int unsigned D = 4,
            parameter int unsigned BW = 2
        ) (
%000009     input clk
        );
          typedef enum logic [1:0] {
            S_IDLE = 2'd0,
            S_RUN = 2'd1,
            S_DONE = 2'd2,
            S_ERR = 2'd3
          } state_t;
        
%000001   logic rst;
%000001   logic start;
          integer cyc;
%000001   state_t state  /*verilator fsm_reset_arc*/;
%000001   logic [1:0] done_arr;
        
%000001   logic [W-1:0] a;
%000000   logic [BW-1:0] b;
          begin
%000001     logic [D-1:0][W-1:0] s;
            begin
%000009       always_ff @(posedge clk) s[b] <= a;
            end
          end
        
%000001   initial begin
%000001     rst = 1'b1;
%000001     start = 1'b0;
%000001     cyc = 0;
          end
        
%000009   always @(posedge clk) begin
%000009     cyc <= cyc + 1;
%000008     if (cyc == 1) rst <= 1'b0;
%000008     if (cyc == 2) start <= 1'b1;
%000008     if (cyc == 3) start <= 1'b0;
%000008     if (cyc == 4) a[0] = 1'b1;
%000008     if (cyc == 8) begin
%000001       $write("*-* All Finished *-*\n");
%000001       $finish;
            end
          end
        
%000009   always_ff @(posedge clk) begin
%000007     if (rst) begin
%000002       state <= S_IDLE;
            end
%000007     else begin
%000007       case (state)
        // [FSM coverage]
%000001        // [fsm_arc t.state::ANY->S_IDLE[reset_include]] [reset arc, excluded from %]
%000002        // [fsm_arc t.state::S_DONE->S_DONE]
%000003        // [fsm_arc t.state::S_IDLE->S_IDLE]
%000001        // [fsm_arc t.state::S_IDLE->S_RUN]
%000001        // [fsm_state t.state::S_DONE]
%000000        // [fsm_state t.state::S_ERR] *** UNCOVERED ***
%000000        // [fsm_state t.state::S_IDLE] *** UNCOVERED ***
%000001        // [fsm_state t.state::S_RUN]
%000002         S_IDLE:
%000001         if (start) state <= S_RUN;
%000001         else state <= S_IDLE;
%000003         S_RUN: begin
                  ;
%000003           done_arr[0] <= (a[0] == 1'b1);
%000002           if (done_arr[0]) begin
%000001             state <= S_DONE;
                  end
%000002           else begin
%000002             state <= S_RUN;
                  end
                end
%000002         S_DONE: state <= S_DONE;
%000000         default: state <= S_ERR;
              endcase
            end
          end
        
        endmodule