24 lines
422 B
Systemverilog
24 lines
422 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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// verilog_format: off
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sequence s_arg(x);
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@(posedge clk) x;
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endsequence
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// verilog_format: on
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task automatic f;
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bit x = 1;
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@(s_arg(x));
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endtask
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initial f();
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endmodule
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