mirror of https://github.com/zachjs/sv2v.git
148 lines
3.9 KiB
Bash
148 lines
3.9 KiB
Bash
#!/bin/bash
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SCRIPT_DIR=`dirname "${BASH_SOURCE[0]}"`
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SV2V="$SCRIPT_DIR/../../bin/sv2v +RTS -N1 -RTS"
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assertExists() {
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file=$1
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[ -f "$file" ]
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assertTrue "$file does not exist" $?
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}
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# USAGE: simulate <vcd-file> <log-file> <top-module> <file> [<file> ...]
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simulate() {
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# arguments
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sim_vcd=$1
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sim_log=$2
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sim_top=$3
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shift 3
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# compile the files
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sim_prog=$SHUNIT_TMPDIR/simprog.exe
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iv_output=`iverilog \
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-Wall \
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-Wno-select-range \
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-Wno-anachronisms \
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-Wno-portbind \
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-o $sim_prog \
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-g2005 \
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-DTEST_VCD="\"$sim_vcd\"" \
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-DTEST_TOP=$sim_top \
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$SCRIPT_DIR/tb_dumper.v \
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"$@" 2>&1`
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assertTrue "iverilog on $1 failed" $?
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if [ -n "$iv_output" ]; then
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assertNull "iverilog emitted warnings:" "$iv_output"
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echo "$iv_output"
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fi
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# run the simulation
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$sim_prog > $sim_log.temp
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assertTrue "simulating $1 failed" $?
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assertExists $sim_vcd
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# remove the date from the VCD
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sed -i.orig -e "1,3d" $sim_vcd
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# remove extraneous log lines
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cat $sim_log.temp | grep -v "VCD info: dumpfile" > $sim_log
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}
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assertConverts() {
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ac_file=$1
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ac_tmpa=$SHUNIT_TMPDIR/ac-conv-tmpa.v
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$SV2V $ac_file 2> /dev/null > $ac_tmpa
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assertTrue "1st conversion of $ac_file failed" $?
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ac_tmpb=$SHUNIT_TMPDIR/ac-conv-tmpb.v
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$SV2V $ac_tmpa 2> /dev/null > $ac_tmpb
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assertTrue "2nd conversion of $ac_file failed" $?
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diff $ac_tmpa $ac_tmpb > /dev/null
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assertTrue "conversion of $ac_file not stable after the first iteration" $?
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$SV2V -v $ac_file 2> /dev/null > /dev/null
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assertTrue "verbose conversion of $ac_file failed" $?
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# using sed to remove quoted strings and integer unsigned
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filtered=`sed -E -e 's/"([^"]|\")+"//g' -e 's/integer unsigned/integer/g' $ac_tmpa`
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# check for various things iverilog accepts which we don't want to output
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prefix="conversion of $ac_file still contains"
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assertNotMatch "$filtered" "$prefix dimension queries" \
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'\$bits|\$dimensions|\$unpacked_dimensions|\$left|\$right|\$low|\$high|\$increment|\$size'
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assertNotMatch "$filtered" "$prefix SystemVerilog types" \
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'[[:space:]](int|bit|logic|byte|struct|enum|longint|shortint)[[:space:]]'
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assertNotMatch "$filtered" "$prefix unsigned keyword" \
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'[^\$a-zA-Z_]unsigned'
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}
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assertNotMatch() {
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if [[ "$1" =~ $3 ]]; then
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fail "$2"
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fi
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}
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# convert SystemVerilog source file(s)
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convert() {
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out_file=$1; shift
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$SV2V "$@" 2> /dev/null > $out_file
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assertTrue "conversion failed" $?
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}
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simpleTest() {
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sv=$1
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ve=$2
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tb=$3
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assertConverts $sv
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# some tests use inputs compatible with iverilog directly and so omit the
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# reference manually converted file
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if [ ! -f $ve ]; then
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ve=$sv
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else
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assertConverts $ve
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fi
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# some tests don't have a separate testbench, instead having the top-level
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# module defined in both of the input files
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if [ ! -f $tb ]; then
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tb=$SCRIPT_DIR/empty.v
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else
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assertConverts $tb
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fi
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cv=$SHUNIT_TMPDIR/conv.v
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convert $cv $sv
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simulateAndCompare $ve $cv $tb
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}
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simulateAndCompare() {
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ve=$1
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cv=$2
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tb=$3
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ref_vcd=$SHUNIT_TMPDIR/ref.vcd
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gen_vcd=$SHUNIT_TMPDIR/gen.vcd
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ref_log=$SHUNIT_TMPDIR/ref.log
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gen_log=$SHUNIT_TMPDIR/gen.log
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# simulate and compare the two files
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simulate $ref_vcd $ref_log top $ve $tb
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simulate $gen_vcd $gen_log top $cv $tb
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output=`diff $ref_vcd $gen_vcd`
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assertTrue "VCDs are different:\n$output" $?
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output=`diff $ref_log $gen_log`
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assertTrue "Simulation outputs differ:\n$output" $?
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rm -f $ref_vcd
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rm -f $gen_vcd
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rm -f $ref_log
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rm -f $gen_log
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}
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runTest() {
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test=$1
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simpleTest "${test}.sv" "${test}.v" "${test}_tb.v"
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}
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runAndCapture() {
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$SV2V "$@" > "$SHUNIT_TMPDIR/stdout" 2> "$SHUNIT_TMPDIR/stderr"
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result=$?
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stdout=`cat $SHUNIT_TMPDIR/stdout`
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stderr=`cat $SHUNIT_TMPDIR/stderr`
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}
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