mirror of https://github.com/zachjs/sv2v.git
105 lines
2.5 KiB
Systemverilog
105 lines
2.5 KiB
Systemverilog
`define CASE_A(name, dims) \
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module name(clock, in, out); \
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input wire clock, in; \
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output logic dims out; \
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initial out[0] = 0; \
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initial out[1] = 0; \
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initial out[2] = 0; \
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always @(posedge clock) begin \
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\
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out[2][4] = out[2][3]; \
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out[2][3] = out[2][2]; \
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out[2][2] = out[2][1]; \
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out[2][1] = out[2][0]; \
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out[2][0] = out[1][4]; \
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\
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out[1][4] = out[1][3]; \
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out[1][3] = out[1][2]; \
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out[1][2] = out[1][1]; \
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out[1][1] = out[1][0]; \
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out[1][0] = out[0][4]; \
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\
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out[0][4] = out[0][3]; \
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out[0][3] = out[0][2]; \
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out[0][2] = out[0][1]; \
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out[0][1] = out[0][0]; \
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out[0][0] = in; \
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\
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end \
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endmodule
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`CASE_A(A1, [2:0][4:0])
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`CASE_A(A2, [0:2][0:4])
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`CASE_A(A3, [0:2][4:0])
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`CASE_A(A4, [2:0][0:4])
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`define CASE_B(name, dims) \
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module name(clock, in, out); \
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input wire clock, in; \
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output logic dims out; \
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initial out[1] = 0; \
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initial out[2] = 0; \
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initial out[3] = 0; \
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always @(posedge clock) begin \
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\
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out[3][5] = out[3][4]; \
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out[3][4] = out[3][3]; \
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out[3][3] = out[3][2]; \
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out[3][2] = out[3][1]; \
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out[3][1] = out[2][5]; \
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\
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out[2][5] = out[2][4]; \
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out[2][4] = out[2][3]; \
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out[2][3] = out[2][2]; \
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out[2][2] = out[2][1]; \
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out[2][1] = out[1][5]; \
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\
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out[1][5] = out[1][4]; \
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out[1][4] = out[1][3]; \
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out[1][3] = out[1][2]; \
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out[1][2] = out[1][1]; \
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out[1][1] = in; \
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\
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end \
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endmodule
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`CASE_B(B1, [3:1][5:1])
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`CASE_B(B2, [1:3][1:5])
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`CASE_B(B3, [1:3][5:1])
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`CASE_B(B4, [3:1][1:5])
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`define CASE_C(name, dims) \
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module name(clock, in, out); \
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input wire clock, in; \
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output logic dims out; \
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initial out[2] = 0; \
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initial out[3] = 0; \
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initial out[4] = 0; \
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always @(posedge clock) begin \
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\
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out[4][6] = out[4][5]; \
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out[4][5] = out[4][4]; \
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out[4][4] = out[4][3]; \
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out[4][3] = out[4][2]; \
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out[4][2] = out[3][6]; \
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\
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out[3][6] = out[3][5]; \
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out[3][5] = out[3][4]; \
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out[3][4] = out[3][3]; \
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out[3][3] = out[3][2]; \
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out[3][2] = out[2][6]; \
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\
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out[2][6] = out[2][5]; \
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out[2][5] = out[2][4]; \
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out[2][4] = out[2][3]; \
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out[2][3] = out[2][2]; \
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out[2][2] = in; \
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\
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end \
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endmodule
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`CASE_C(C1, [4:2][6:2])
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`CASE_C(C2, [2:4][2:6])
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`CASE_C(C3, [2:4][6:2])
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`CASE_C(C4, [4:2][2:6])
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