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Zachary Snow
33dc4b3f88
- NestTF refactored to cover all package items - fixed issue where type traverse skipped typedefs
18 lines
382 B
Verilog
18 lines
382 B
Verilog
module top;
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task foo;
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$display("task foo() called");
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endtask
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function bar;
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input [2:0] n;
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bar = baz(n + 1);
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endfunction
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function baz;
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input [2:0] n;
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baz = n * 2;
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endfunction
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localparam PARAM = 37;
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initial foo();
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initial $display("bar(0) = %d", bar(0));
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initial $display("PARAM = %d", PARAM);
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endmodule
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