mirror of
https://github.com/zachjs/sv2v.git
synced 2026-09-08 12:53:12 +02:00
8 lines
121 B
Verilog
8 lines
121 B
Verilog
(* a=1 *) module top;
|
|
(* foo="bar" *) reg x;
|
|
initial begin
|
|
x = 1;
|
|
$display(x);
|
|
end
|
|
endmodule
|