mirror of https://github.com/zachjs/sv2v.git
27 lines
680 B
Verilog
27 lines
680 B
Verilog
module top;
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reg inp1, inp2;
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wire out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB;
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mod m(inp1, inp2, out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB);
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initial begin
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$monitor(inp1, inp2,
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out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB);
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repeat (2) begin
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#1 inp1 = 0;
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#1 inp2 = 0;
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#1 inp2 = 1;
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#1 inp1 = 1;
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#1 inp2 = 0;
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#1 inp2 = 1;
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#1 inp2 = 0;
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#1 inp1 = 0;
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#1 inp1 = 1;
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#1 inp2 = 1;
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#1 inp1 = 0;
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#1 inp1 = 1;
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end
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end
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endmodule
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