mirror of https://github.com/zachjs/sv2v.git
77 lines
1.5 KiB
Verilog
77 lines
1.5 KiB
Verilog
module mod(
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input wire inp1, inp2,
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output reg out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB
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);
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localparam ZERO = 0;
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task automatic t;
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output reg o;
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o = inp1;
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endtask
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function automatic flop;
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input reg i;
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flop = i;
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endfunction
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function automatic flip;
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input reg i;
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flip = flop(~i);
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endfunction
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function automatic f;
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input reg i; // ignored
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f = inp2;
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endfunction
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function automatic g;
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input reg i; // ignored
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g = f(ZERO) & inp1;
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endfunction
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task automatic u;
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output reg o;
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o = inp1;
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endtask
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task automatic asgn;
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output reg o;
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input reg i;
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o = i;
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endtask
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always @*
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t(out1);
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always @(inp2)
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out2 = f(ZERO);
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always @(inp1, inp2)
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out3 = f(ZERO) & inp1;
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always @(inp1, inp2)
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out4 = g(ZERO);
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always @*
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out5 = flip(inp1);
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always @(inp1, inp2) begin : blk
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reg x;
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x = g(ZERO);
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out6 = x;
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end
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always @(inp1)
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u(out7);
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parameter ONE = 1;
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if (ONE)
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always @(inp1, inp2) begin
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asgn(out8, flip(inp1));
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out9 = f(ZERO);
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end
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always @(inp1, inp2)
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if (inp1)
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outA = f(ZERO);
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wire [1:0] s;
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assign s = {inp1, inp2};
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function automatic h;
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input reg i; // ignored
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h = s[0];
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endfunction
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always @(s[0])
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outB = h(ZERO);
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endmodule
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