mirror of https://github.com/zachjs/sv2v.git
18 lines
387 B
Systemverilog
18 lines
387 B
Systemverilog
module top;
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wire [3:0] a, b, w, x, y, z;
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assign a = 4'b1011;
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assign b = 4'b0101;
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// loses upper bits
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assign w = (a * b) >> 4;
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// preserves upper bits via implicit extension
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assign x = (1 * a * b) >> 4;
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assign y = (a * b * 1) >> 4;
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// preserves upper bits via "casting"
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wire [7:0] tmp;
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assign tmp = a * b;
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assign z = tmp >> 4;
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endmodule
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