mirror of https://github.com/zachjs/sv2v.git
56 lines
1.6 KiB
Systemverilog
56 lines
1.6 KiB
Systemverilog
`define CASE(name, dims, a, b) \
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module name(clock, in, out); \
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input wire clock, in; \
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output logic dims out; \
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initial out[0+a] = 0; \
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initial out[1+a] = 0; \
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initial out[2+a] = 0; \
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always @(posedge clock) begin \
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/*$display($time, `" name ", out[0+a][1+b+:1]);*/ \
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/*$display($time, `" name ", out[0+a][1+b+:1]);*/ \
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/*$display($time, `" name ", out[1+a][1+b+:1]);*/ \
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/*$display($time, `" name ", out[1+a][1+b+:1]);*/ \
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/*$display($time, `" name ", out[2+a][1+b+:1]);*/ \
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/*$display($time, `" name ", out[2+a][1+b+:1]);*/ \
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\
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out[2+a][4+b] = out[2+a][3+b]; \
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out[2+a][3+b] = out[2+a][2+b]; \
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out[2+a][2+b] = out[2+a][1+b]; \
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out[2+a][1+b] = out[2+a][0+b]; \
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out[2+a][0+b] = out[1+a][4+b]; \
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\
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out[1+a][4+b] = out[1+a][3+b]; \
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out[1+a][3+b] = out[1+a][2+b]; \
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out[1+a][2+b] = out[1+a][1+b]; \
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out[1+a][1+b] = out[1+a][0+b]; \
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out[1+a][0+b] = out[0+a][4+b]; \
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\
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out[0+a][4+b] = out[0+a][3+b]; \
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out[0+a][3+b] = out[0+a][2+b]; \
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out[0+a][2+b] = out[0+a][1+b]; \
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out[0+a][1+b] = out[0+a][0+b]; \
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out[0+a][0+b] = in; \
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\
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end \
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endmodule
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`CASE(A1, [2:0][4:0], 0, 0)
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`CASE(A2, [0:2][0:4], 0, 0)
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`CASE(A3, [0:2][4:0], 0, 0)
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`CASE(A4, [2:0][0:4], 0, 0)
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`CASE(B1, [3:1][5:1], 1, 1)
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`CASE(B2, [1:3][1:5], 1, 1)
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`CASE(B3, [1:3][5:1], 1, 1)
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`CASE(B4, [3:1][1:5], 1, 1)
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`CASE(C1, [4:2][6:2], 2, 2)
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`CASE(C2, [2:4][2:6], 2, 2)
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`CASE(C3, [2:4][6:2], 2, 2)
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`CASE(C4, [4:2][2:6], 2, 2)
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`CASE(D1, [5:3][6:2], 3, 2)
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`CASE(D2, [3:5][2:6], 3, 2)
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`CASE(D3, [3:5][6:2], 3, 2)
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`CASE(D4, [5:3][2:6], 3, 2)
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