mirror of https://github.com/zachjs/sv2v.git
15 lines
449 B
Verilog
15 lines
449 B
Verilog
module top;
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localparam [31:0] init_val = {8'd0, 8'd8, 8'd10, 8'd200};
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initial begin : foo
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integer i, j;
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for (i = 3; i >= 0; i -= 1) begin
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$display(init_val[8*i+:8]);
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for (j = 0; j < 8; j += 1) begin
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$display(init_val[8*i+j]);
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end
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end
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end
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localparam [23:0] X = { 8'd5, 8'd3, 8'd2 };
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initial $display("%0d %0d %0d", X[16+:8], X[8+:8], X[0+:8]);
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endmodule
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