mirror of https://github.com/zachjs/sv2v.git
28 lines
931 B
Verilog
28 lines
931 B
Verilog
module wrap;
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initial begin
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// This was generated by running the original through VCS.
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$display(" 0 01101 01101");
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$display(" 10 11101 11101");
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$display(" 20 01101 01101");
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$display(" 30 11101 11101");
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$display(" 40 01101 01101");
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$display(" 50 11101 11101");
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$display(" 60 01101 01101 {011 01} 01101 {01 101}");
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$display(" 70 11001 11001 {110 01} 11001 {11 001}");
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$display(" 80 01110 01110 {011 10} 01110 {01 110}");
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$display(" 90 01010 01010 {010 10} 01010 {01 010}");
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$display(" 110 11010 11010 {110 10} 11010 {11 010}");
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$display(" 120 11101 11101 {111 01} 11101 {11 101}");
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#130;
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end
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endmodule
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