mirror of https://github.com/zachjs/sv2v.git
24 lines
536 B
Verilog
24 lines
536 B
Verilog
`define DUMP(id) \
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begin \
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x = 1'sb1; \
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$display(`"id: access a=%b b=%b`", x[0+:A], x[A+:B]); \
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x = { {A {1'sb1}}, {B {1'sbz}} }; \
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$display(`"id: literal x=%b`", x); \
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end
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module top;
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parameter A = 2;
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parameter B = 3;
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reg [A+B-1:0] x;
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initial `DUMP(0)
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if (1) begin : blk
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localparam _A = 10;
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localparam _B = 11;
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initial `DUMP(1)
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end
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initial begin : foo
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localparam _A = 10;
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localparam _B = 11;
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`DUMP(2)
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end
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endmodule
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