mirror of https://github.com/zachjs/sv2v.git
145 lines
4.3 KiB
Verilog
145 lines
4.3 KiB
Verilog
module top;
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initial begin
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$display("packet addr = %b", {2'b01, 2'b10});
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$display("packet data = %b", {2'b00, 2'b11});
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end
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task printer;
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input [23:0] inpA;
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input [23:0] inpB;
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$display("printer(%h, %h)", inpA, inpB);
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endtask
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function automatic [23:0] pack_r_8_24;
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input [23:0] in;
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integer i;
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for (i = 0; i < 24; i = i + 8) begin
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pack_r_8_24[i+:8] = in[i+:8];
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end
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endfunction
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function automatic [23:0] pack_l_8_24;
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input [23:0] in;
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integer i;
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for (i = 0; i < 24; i = i + 8) begin
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pack_l_8_24[i+:8] = in[23-i-:8];
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end
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endfunction
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function automatic [23:0] pack_r_1_24;
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input [23:0] in;
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integer i;
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for (i = 0; i < 24; i = i + 1) begin
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pack_r_1_24[i] = in[i];
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end
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endfunction
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function automatic [23:0] pack_l_1_24;
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input [23:0] in;
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integer i;
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for (i = 0; i < 24; i = i + 1) begin
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pack_l_1_24[i] = in[23-i];
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end
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endfunction
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function automatic [23:0] pack_r_7_24;
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input [23:0] in;
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integer i;
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for (i = 0; i < 24; i = i + 7) begin
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pack_r_7_24[i+:7] = in[i+:7];
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end
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endfunction
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function automatic [23:0] pack_l_7_24;
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input [23:0] in;
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integer i;
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begin
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for (i = 0; i + 7 < 24; i = i + 7) begin
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pack_l_7_24[23-i-:7] = in[i+:7];
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end
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pack_l_7_24[0+:24%7] = in[i+:24%7];
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end
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endfunction
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initial begin
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$display("%h", pack_r_8_24(24'h060708));
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$display("%h", pack_l_8_24(24'h060708));
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$display("%h", pack_r_1_24(24'h060708));
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$display("%h", pack_l_1_24(24'h060708));
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$display("%h", pack_r_7_24(24'h060708));
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$display("%h", pack_l_7_24(24'h060708));
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$display("%h", pack_r_7_24(24'h607080));
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$display("%h", pack_l_7_24(24'h0c0708));
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$display("%h", pack_r_7_24(24'h070800));
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$display("%h", pack_l_7_24(24'h000708));
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$display("%h", pack_r_7_24(24'h070800));
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$display("%h", pack_l_7_24(24'h000708));
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printer(pack_r_7_24(24'h070800), pack_l_7_24(24'h000708));
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end
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reg [23:0] init_simple_stream_var = pack_l_7_24(24'h000718);
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wire [23:0] init_simple_stream_net = pack_l_7_24(24'h000728);
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reg [23:0] init_indirect_stream_var = pack_l_7_24(24'h000738);
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wire [23:0] init_indirect_stream_net = pack_l_7_24(24'h000748);
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reg [23:0] asgn_simple_stream_var = pack_l_7_24(24'h000758);
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wire [23:0] asgn_simple_stream_net = pack_l_7_24(24'h000768);
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reg [23:0] asgn_indirect_stream_var = pack_l_7_24(24'h000778);
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wire [23:0] asgn_indirect_stream_net = pack_l_7_24(24'h000788);
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initial begin
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#1;
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$display("%b", init_simple_stream_var);
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$display("%b", init_simple_stream_net);
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$display("%b", init_indirect_stream_var);
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$display("%b", init_indirect_stream_net);
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$display("%b", asgn_simple_stream_var);
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$display("%b", asgn_simple_stream_net);
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$display("%b", asgn_indirect_stream_var);
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$display("%b", asgn_indirect_stream_net);
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end
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task test_unpack;
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input [23:0] in;
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reg [0:0] i;
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reg [1:0] j;
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reg [2:0] k;
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reg [5:0] l;
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reg [11:0] m;
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begin
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{i, j, k, l, m} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{i, j, k, l, m} = pack_l_8_24(in);
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$display("%b %b %b %b %b", i, j, k, l, m);
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{i, j, k, l, m} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{i, j, k, l, m} = pack_l_1_24(in);
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$display("%b %b %b %b %b", i, j, k, l, m);
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{i, j, k, l, m} = in;
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$display("%b %b %b %b %b", i, j, k, l, m);
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{i, j, k, l, m} = pack_l_7_24(in);
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$display("%b %b %b %b %b", i, j, k, l, m);
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end
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endtask
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initial begin
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test_unpack(24'h060708);
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test_unpack(24'hC02375);
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test_unpack(24'h12E3B8);
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end
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wire [0:0] i;
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wire [1:0] j;
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wire [2:0] k;
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wire [5:0] l;
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wire [11:0] m;
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reg [23:0] in;
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assign {i, j, k, l, m} = pack_l_7_24(in);
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initial begin
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#1 in = 24'h060708;
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#1 in = 24'hC02375;
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#1 in = 24'h12E3B8;
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end
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endmodule
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