mirror of https://github.com/zachjs/sv2v.git
235 lines
4.3 KiB
Verilog
235 lines
4.3 KiB
Verilog
module test;
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reg [31:0] a_w, a_x;
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reg [7:0] a_y;
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reg a_z;
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reg [72:0] a;
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always @* a = {a_w, a_x, a_y, a_z};
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initial begin
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$monitor("%2d: %b %b %b %b %b", $time, a, a_w, a_x, a_y, a_z);
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#1 a_w = 0;
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#1 a_x = 0;
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#1 a_y = 0;
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#1 a_z = 0;
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#1 begin
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a_w = 1;
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a_x = 1;
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a_y = 1;
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a_z = 1;
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end
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#1 begin
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a_w = 2;
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a_x = 2;
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a_y = 2;
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a_z = 2;
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end
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#1 begin
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a_w = 3;
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a_x = 3;
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a_y = 3;
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a_z = 3;
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end
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#1 begin
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a_w = 0;
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a_x = 0;
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a_y = 0;
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a_z = 0;
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end
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#1 begin
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a_w = -1;
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a_x = -1;
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a_y = -1;
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a_z = -1;
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end
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#1 begin
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a_w = -2;
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a_x = -2;
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a_y = -2;
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a_z = -2;
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end
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#1 begin
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a_w = 0;
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a_x = 0;
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a_y = 1;
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a_z = 1;
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end
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#1 begin
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a_w = 1;
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a_x = 1;
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a_y = 0;
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a_z = 1;
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end
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#1 begin
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a_w = 1;
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a_x = 1;
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a_y = 1;
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a_z = 0;
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end
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#1 begin
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a_w = 2;
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a_x = 2;
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a_y = 3;
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a_z = 1;
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end
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#1;
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#1 begin
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a_w = 3;
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a_x = 3;
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a_y = 2;
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a_z = 0;
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end
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#1 begin
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a_w = 8;
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a_x = 0;
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a_y = 1;
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a_z = 1;
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end
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#1 begin
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a_w = 8;
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a_x = 1;
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a_y = 0;
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a_z = 1;
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end
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#1 begin
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a_w = 8;
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a_x = 1;
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a_y = 1;
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a_z = 0;
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end
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#1 begin
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a_w = 8;
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a_x = 2;
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a_y = 3;
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a_z = 1;
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end
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#1;
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#1 begin
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a_w = 8;
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a_x = 3;
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a_y = 2;
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a_z = 0;
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end
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end
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reg [31:0] b_x;
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wire [72:0] b_y;
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reg b_z;
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reg [105:0] b;
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assign b_y = a;
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always @* b = {b_x, b_y, b_z};
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initial begin
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#100;
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a_w = 'bx;
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a_x = 'bx;
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a_y = 'bx;
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a_z = 'bx;
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$monitor("%2d: %b %b %b %b", $time, b, b_x, b_y, b_z);
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#1 b_x = 0;
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#1 begin
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a_w = 0;
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a_x = 0;
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a_y = 0;
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a_z = 0;
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end
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#1 b_z = 0;
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#1 begin
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a_w = 1;
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a_x = 1;
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a_y = 1;
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a_z = 1;
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b_x = 1;
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b_z = 1;
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end
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#1 begin
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a_w = 2;
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a_x = 2;
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a_y = 2;
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a_z = 2;
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b_x = 2;
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b_z = 2;
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end
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#1 begin
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a_w = 3;
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a_x = 3;
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a_y = 3;
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a_z = 3;
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b_x = 3;
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b_z = 3;
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end
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#1 begin
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a_w = 0;
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a_x = 0;
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a_y = 0;
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a_z = 0;
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b_x = 0;
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b_z = 0;
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end
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#1 begin
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a_w = -1;
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a_x = -1;
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a_y = -1;
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a_z = -1;
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b_x = -1;
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b_z = -1;
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end
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#1 begin
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a_w = -2;
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a_x = -2;
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a_y = -2;
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a_z = -2;
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b_x = -2;
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b_z = -2;
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end
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#1 begin
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a_w = 0;
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a_x = 0;
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a_y = 1;
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a_z = 1;
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b_x = 0;
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b_z = 1;
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end
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#1 begin
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a_w = 1;
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a_x = 1;
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a_y = 0;
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a_z = 1;
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b_x = 1;
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b_z = 1;
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end
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#1 begin
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a_w = 1;
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a_x = 1;
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a_y = 1;
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a_z = 0;
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b_x = 1;
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b_z = 0;
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end
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#1 begin
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a_w = 2;
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a_x = 2;
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a_y = 3;
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a_z = 1;
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b_x = 2;
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b_z = 1;
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end
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#1;
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#1 begin
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a_w = 3;
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a_x = 3;
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a_y = 2;
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a_z = 0;
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b_x = 3;
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b_z = 0;
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end
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end
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endmodule
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module top; endmodule
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