mirror of https://github.com/zachjs/sv2v.git
10 lines
290 B
Verilog
10 lines
290 B
Verilog
module top #(parameter FOO = 10);
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initial $display(FOO);
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endmodule
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module top2 #(parameter FOO = 10, parameter BAR = 11);
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initial $display(FOO, BAR);
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endmodule
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module top3 #(parameter FOO = 10, parameter BAR = 11, parameter BAZ = 12);
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initial $display(FOO, BAR, BAZ);
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endmodule
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