mirror of https://github.com/zachjs/sv2v.git
16 lines
434 B
Verilog
16 lines
434 B
Verilog
module top;
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reg arr [1:0][2:0][3:0];
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initial begin : block_name
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integer i, j, k;
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for (i = 0; i <= 1; i++) begin
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for (j = 0; j <= 2; j++) begin
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for (k = 0; k <= 3; k++) begin
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$display("%b", arr[i][j][k]);
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arr[i][j][k] = i+j+k;
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$display("%b", arr[i][j][k]);
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end
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end
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end
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end
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endmodule
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