mirror of https://github.com/zachjs/sv2v.git
13 lines
354 B
Verilog
13 lines
354 B
Verilog
module top;
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reg [31:0] arr;
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wire [7:0] idx;
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assign idx = { 2'b01, 2'b11, 2'b00, 2'b10 };
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initial begin
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arr[idx[0 * 2 +: 2] * 8 +: 8] = 8'hDE;
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arr[idx[1 * 2 +: 2] * 8 +: 8] = 8'hAD;
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arr[idx[2 * 2 +: 2] * 8 +: 8] = 8'hBE;
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arr[idx[3 * 2 +: 2] * 8 +: 8] = 8'hEF;
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$display("%h", arr);
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end
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endmodule
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