mirror of https://github.com/zachjs/sv2v.git
47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
module Example;
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initial
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$monitor("%b %b %b %b %b %b %b %b %b",
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arr1, arr2, arr3,
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arr4, arr5, arr6,
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arr7, arr8, arr9
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);
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reg [14:0] arr1;
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reg [14:0] arr2;
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reg [14:0] arr3;
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initial begin
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#1; arr1 = 'b100101010100100;
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#1; arr1[0*3+1] = ~arr1[0*3+1];
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#1; arr1[4*3+2] = ~arr1[4*3+2];
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#1; arr2 = 'b100101000110101;
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#1; arr3 = 'b100100111101010;
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#1; arr3[1*3+:3] = arr3[2*3+:3];
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end
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reg [14:0] arr4;
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reg [14:0] arr5;
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reg [14:0] arr6;
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initial begin
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#1; arr4 = 'b100101010100100;
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#1; arr4[0*3+1] = ~arr4[0*3+1];
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#1; arr4[4*3+2] = ~arr4[4*3+2];
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#1; arr5 = 'b100101000110101;
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#1; arr6 = 'b100100111101010;
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#1; arr6[1*3+:3] = arr6[2*3+:3];
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end
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reg [14:0] arr7;
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reg [14:0] arr8;
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reg [14:0] arr9;
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initial begin
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#1; arr7 = 'b100101010100100;
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#1; arr7[(4-0)*3+1] = ~arr7[(4-0)*3+1];
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#1; arr7[(4-4)*3+2] = ~arr7[(4-4)*3+2];
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#1; arr8 = 'b100101000110101;
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#1; arr9 = 'b100100111101010;
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#1; arr9[(4-1)*3+:3] = arr9[(4-2)*3+:3];
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end
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endmodule
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