mirror of https://github.com/zachjs/sv2v.git
48 lines
897 B
Verilog
48 lines
897 B
Verilog
module top;
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reg x, y;
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wire z;
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task t;
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x = 1;
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endtask
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function f;
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input x;
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begin
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y = 1;
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f = 0;
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end
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endfunction
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assign z = 0;
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initial begin
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t;
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$display("%b %b %b %b", x, y, z, f(0));
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$display("%b %b %b %b", x, y, z, f(0));
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end
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generate
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if (1) begin : A
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wire x;
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if (1) begin : B
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reg x;
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end
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if (1) begin : C
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wire x;
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end
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assign x = B.x ^ C.x;
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end
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endgenerate
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initial A.B.x = 0;
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assign A.C.x = 1;
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initial $display("%b %b %b %b", x, A.x, A.B.x, A.C.x);
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reg t2l;
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task t2;
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input reg t2l;
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top.t2l = t2l;
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endtask
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initial begin
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$display("%b", t2l);
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t2(1);
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$display("%b", t2l);
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end
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endmodule
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