mirror of https://github.com/zachjs/sv2v.git
24 lines
501 B
Systemverilog
24 lines
501 B
Systemverilog
interface Interface;
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logic x;
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endinterface
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module ModuleC(Interface intf, input y);
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initial $display("ModuleC %b %b", intf.x, y);
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endmodule
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module ModuleB(Interface intf, input y);
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initial $display("ModuleB %b %b", intf.x, y);
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ModuleC m[2:0] (intf, y);
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endmodule
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module ModuleA(Interface intf, input y);
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initial $display("ModuleA %b %b", intf.x, y);
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ModuleB m[2:0] (intf, y);
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endmodule
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module top;
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logic y;
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Interface intf();
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ModuleA m[2:0] (intf, y);
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endmodule
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