mirror of https://github.com/zachjs/sv2v.git
30 lines
723 B
Verilog
30 lines
723 B
Verilog
module Tester(input clock);
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parameter WIDTH = 1;
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localparam DATA_WIDTH = 2 ** WIDTH;
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reg [2*DATA_WIDTH-1:0] x;
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initial x = 1;
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wire [WIDTH-1:0] idx1, idx2;
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assign idx1 = $clog2(x[2*DATA_WIDTH-1:DATA_WIDTH]);
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assign idx2 = $clog2(x[DATA_WIDTH-1:0]);
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integer i = 0;
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initial #1 $display("shadow i = %d, %b", i, x);
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always @(posedge clock) begin : block
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localparam SIZE = 2 * DATA_WIDTH;
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integer i;
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reg temp;
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temp = x[SIZE-1];
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for (i = SIZE-1; i > 0; i = i - 1) begin
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x[i] = x[i-1];
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end
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x[0] = temp;
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end
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always @(negedge clock)
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$display("%d %0d %2d %2d %b", $time, WIDTH, idx1, idx2, x);
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endmodule
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