mirror of https://github.com/zachjs/sv2v.git
58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
module ClientAnd (client_req, bits);
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parameter WIDTH = 2;
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output client_req;
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input [WIDTH-1:0] bits;
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assign client_req = &bits;
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endmodule
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module ClientTick #(
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parameter start = 0,
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parameter period = 1
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) (
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output reg client_req,
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input clock
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);
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initial client_req = start;
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integer counter;
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initial counter = 0;
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always @(posedge clock) begin
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counter += 1;
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if (counter % period == 0)
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client_req = ~client_req;
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end
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endmodule
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module top;
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reg clock;
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initial begin
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clock = 1;
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forever #1 clock = ~clock;
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end
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parameter N = 8;
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generate
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if (1) begin : intf
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wire [N-1:0] req;
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end
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genvar j;
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for (j = 0; j < N - 1; j = j + 1) begin : clients
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ClientTick #(j, j + 1) client(
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.clock,
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.client_req(intf.req[j + 1])
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);
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end
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endgenerate
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ClientAnd #(4) client(
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.bits(intf.req[4:1]),
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.client_req(intf.req[0])
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);
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initial begin
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$monitor("%0d %b %b", $time, clock, intf.req);
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#100 $finish;
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end
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endmodule
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