mirror of https://github.com/zachjs/sv2v.git
54 lines
1.4 KiB
Verilog
54 lines
1.4 KiB
Verilog
module Test();
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parameter BASE = 0;
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parameter SIZE = 0;
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parameter DIR = 0;
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localparam LEFT = BASE;
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localparam RIGHT = BASE + DIR * (SIZE - 1);
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genvar left, right, offset;
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generate
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for (left = LEFT + SIZE; left <= RIGHT + SIZE; left = left + 1)
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for (right = LEFT + SIZE; right <= RIGHT + SIZE; right = right + 1)
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if ((left - right) * DIR <= 0)
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for (offset = -2 + SIZE; offset <= 2 + SIZE; offset = offset + 1)
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begin
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Instance #(
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LEFT, RIGHT,
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left - SIZE, right - SIZE, offset - SIZE
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) i();
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initial begin
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i.xs = 1;
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while (i.xs != 0) begin
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#1;
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$display("LEFT=%2d RIGHT=%2d INNER_LEFT=%2d INNER_RIGHT=%2d INNER_OFFSET=%2d i.xs=%b i.l.xs=%b i.m.xs=%b i.n.xs=%b",
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LEFT, RIGHT,
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left - SIZE, right - SIZE, offset - SIZE,
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i.xs, i.l.xs, i.m.xs, i.n.xs);
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i.xs = i.xs + 1;
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end
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end
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end
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endgenerate
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endmodule
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module Suite();
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parameter SIZE = 0;
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genvar base;
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generate
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for (base = -2 + SIZE; base <= 2 + SIZE; base = base + 1) begin
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Test #(base - SIZE, SIZE, -1) b();
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Test #(base - SIZE, SIZE, 1) f();
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end
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endgenerate
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endmodule
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module top;
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Suite #(2) s2();
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Suite #(3) s3();
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Suite #(4) s4();
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endmodule
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