mirror of https://github.com/zachjs/sv2v.git
30 lines
756 B
Verilog
30 lines
756 B
Verilog
module top;
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reg [7:0] foo = {2'b10,2'b01,2'b11,2'b00};
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initial begin : f
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integer x;
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for (x = 0; x <= 3; x = x + 1)
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$display(x, foo[6 - 2*x+:2]);
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end
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reg [32*2*3*4 - 1:0] A;
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reg [5*4*4*2 + 32: 1 + 32] B;
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initial begin
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A = 0;
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B = 0;
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begin : g
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integer i, j, k;
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for (i = 0; i <= 1; i = i + 1)
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for (j = 0; j <= 2; j = j + 1)
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for (k = 0; k <= 3; k = k + 1)
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$display(i, j, k);
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end
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begin : h
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integer q, r, s;
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for (q = 5; q >= 1; q = q - 1)
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for (r = 0; r <= 3; r = r + 1)
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for (s = 2; s >= 1; s = s - 1)
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$display(q, r, s);
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end
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end
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endmodule
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