mirror of https://github.com/zachjs/sv2v.git
71 lines
2.2 KiB
Verilog
71 lines
2.2 KiB
Verilog
module top;
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wire t;
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initial $display("A t %0d", 1);
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initial $display("A top.t %0d", 1);
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generate
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if (1) begin : X
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wire [1:0] t;
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initial $display("B t %0d", 2);
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initial $display("B top.t %0d", 1);
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initial $display("B X.t %0d", 2);
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initial $display("B top.X.t %0d", 2);
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if (1) begin : Y
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wire [2:0] t;
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initial $display("C t %0d", 3);
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initial $display("C top.t %0d", 1);
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initial $display("C X.t %0d", 2);
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initial $display("C top.X.t %0d", 2);
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initial $display("C Y.t %0d", 3);
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initial $display("C X.Y.t %0d", 3);
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initial $display("C top.X.Y.t %0d", 3);
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end
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end
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genvar i;
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for (i = 0; i < 3; i = i + 1) begin : Z
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wire [i:0] t;
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end
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endgenerate
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initial $display("A t %0d", 1);
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initial $display("A top.t %0d", 1);
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initial $display("A X.t %0d", 2);
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initial $display("A top.X.t %0d", 2);
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initial $display("A X.Y.t %0d", 3);
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initial $display("A top.X.Y.t %0d", 3);
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initial $display("A top.Z[0].t %0d", 1);
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initial $display("A Z[0].t %0d", 1);
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initial $display("A Z[1].t %0d", 2);
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initial $display("A Z[2].t %0d", 3);
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wire x;
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initial begin : name
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reg [1:0] x;
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reg [5:0] y;
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$display("size of x = %0d", $bits(x));
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$display("size of y = %0d", $bits(y));
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end
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wire [11:0] arr;
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generate
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if (1) begin : M
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wire [19:0] arr;
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initial $display("M arr[0] = %b", arr[4:0]);
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initial $display("M M.arr[0] = %b", M.arr[4:0]);
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initial $display("M top.arr[0] = %b", top.arr[3:0]);
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end
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endgenerate
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initial $display("arr[0] = %b", arr[3:0]);
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initial $display("M.arr[0] = %b", M.arr[4:0]);
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initial $display("top.arr[0] = %b", top.arr[3:0]);
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localparam [0:5] arr2 = 6'b011100;
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generate
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genvar j;
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for (i = 0 ; i < 2 ; i = i + 1) begin
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for (j = 0 ; j < 3 ; j = j + 1) begin
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localparam value = arr2[i * 3 + j];
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initial $display("%0d %0d %0d", i, j, value);
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end
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end
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endgenerate
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endmodule
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