mirror of https://github.com/zachjs/sv2v.git
20 lines
453 B
Verilog
20 lines
453 B
Verilog
module top;
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function automatic [31:0] lcg(input [31:0] x);
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begin : foo
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reg [3:0] temp;
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lcg = x;
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for (temp = 0; temp < 3; temp++) begin
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lcg *= 1664525;
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lcg += 1013904223;
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end
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end
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endfunction
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initial $display(lcg(0));
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initial $display(lcg(1));
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initial $display(lcg(2));
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initial $display(lcg(3));
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initial $display(lcg(4));
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initial $display(lcg(5));
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endmodule
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