mirror of https://github.com/zachjs/sv2v.git
13 lines
391 B
Verilog
13 lines
391 B
Verilog
module top;
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localparam [11:0] ARR = 12'h3EA;
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initial begin : foo
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integer i, j;
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for (i = 0; i < 4; ++i)
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for (j = 0; j < 3; ++j)
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$display("ARR[%0d][%0d] = %0d", i, j, ARR[i * 3 + j]);
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for (i = 0; i < 4; ++i)
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for (j = 0; j < 3; ++j)
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$display("ARR[%0d][%0d] = %0d", i, j, ARR[i * 3 + j]);
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end
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endmodule
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