mirror of https://github.com/zachjs/sv2v.git
43 lines
1.0 KiB
Verilog
43 lines
1.0 KiB
Verilog
`define FOO(tag) \
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wire [14:0] tag``one_out, tag``two_out, tag``thr_out, tag``fou_out; \
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tag``1 tag``one(.clock(clock), .in(in), .out(tag``one_out)); \
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tag``2 tag``two(.clock(clock), .in(in), .out(tag``two_out)); \
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tag``3 tag``thr(.clock(clock), .in(in), .out(tag``thr_out)); \
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tag``4 tag``fou(.clock(clock), .in(in), .out(tag``fou_out)); \
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integer tag``i; \
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initial begin \
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for (tag``i = 0; tag``i < 20; tag``i++) begin \
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#2; \
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$display(`"tag`", $time, ": %h %15b %15b %15b %15b", in, \
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tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
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end \
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end
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module top;
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reg clock, in;
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initial begin
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clock = 1;
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forever #1 clock = ~clock;
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end
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integer i;
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localparam [20:0] pattern = 20'b01101100001010101100;
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initial begin
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for (i = 0; i < 20; i++) begin
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in = pattern[i];
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#2;
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end
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$finish;
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end
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`FOO(A)
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`FOO(B)
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`FOO(C)
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`FOO(D)
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`FOO(E)
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`FOO(F)
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`FOO(G)
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endmodule
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