mirror of https://github.com/zachjs/sv2v.git
29 lines
966 B
Haskell
29 lines
966 B
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for splitting up complex port declarations. VTR doesn't support:
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- `input wire foo;` but does suport: `input foo; wire foo;`.
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-}
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module Convert.SplitPortDecl (convert) where
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: AST -> AST
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convert = traverseDescriptions convertDescription
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convertDescription :: Description -> Description
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convertDescription (Module name ports items) =
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Module name ports (concat $ map splitPortDecl items)
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convertDescription other = other
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splitPortDecl :: ModuleItem -> [ModuleItem]
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splitPortDecl (orig @ (MIDecl (Variable Local _ _ _ _))) = [orig]
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splitPortDecl (orig @ (MIDecl (Variable _ (Implicit _) _ _ _))) = [orig]
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splitPortDecl (MIDecl (Variable d t x a me)) =
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[ MIDecl $ Variable d (Implicit r) x a Nothing
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, MIDecl $ Variable Local t x a me ]
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where (_, r) = typeDims t
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splitPortDecl other = [other]
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