mirror of https://github.com/zachjs/sv2v.git
47 lines
1.6 KiB
Haskell
47 lines
1.6 KiB
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for `logic`
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-}
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-- Regarding `logic` conversion: The SystemVerilog grammar has the concept of a
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-- `data_declaration`, which seems to cover things much more generally. While
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-- obviously `logic` can appear as module items or ports, they can also be
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-- function arguments, for example.
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-- It seems like logic only becomes reg if it is assigned to in an always block.
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module Convert.Logic (convert) where
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import Control.Monad.Writer
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import qualified Data.Set as Set
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import Convert.Traverse
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import Language.SystemVerilog.AST
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type RegIdents = Set.Set String
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convert :: AST -> AST
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convert = traverseDescriptions convertDescription
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convertDescription :: Description -> Description
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convertDescription orig =
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traverseModuleItems convertModuleItem orig
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where
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idents = execWriter (collectModuleItemsM regIdents orig)
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convertModuleItem :: ModuleItem -> ModuleItem
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convertModuleItem (MIDecl (Variable dir (Logic mr) ident a me)) =
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MIDecl $ Variable dir (t mr) ident a me
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where t = if Set.member ident idents then Reg else Wire
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convertModuleItem other = other
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regIdents :: ModuleItem -> Writer RegIdents ()
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regIdents (AlwaysC _ stmt) = collectStmtLHSsM idents stmt
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where
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idents :: LHS -> Writer RegIdents ()
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idents (LHS vx ) = tell $ Set.singleton vx
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idents (LHSBit vx _) = tell $ Set.singleton vx
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idents (LHSRange vx _) = tell $ Set.singleton vx
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idents (LHSConcat lhss) = mapM idents lhss >>= \_ -> return ()
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regIdents _ = return ()
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