mirror of https://github.com/zachjs/sv2v.git
27 lines
531 B
Systemverilog
27 lines
531 B
Systemverilog
`define TEST(value) \
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logic [63:0] val_``value = 'value; \
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initial $display(`"'value -> %b %b", val_``value, 'value);
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module top;
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`TEST(1);
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`TEST(0);
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`TEST(x);
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`TEST(z);
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logic flag;
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logic [31:0] i;
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] c;
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initial begin
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i = 42;
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flag = 1;
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a = (flag ? '1 : i);
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b = (flag ? 'x : i);
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c = (flag ? '1 : '0);
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$display("%b", a);
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$display("%b", b);
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$display("%b", c);
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end
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endmodule
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