mirror of https://github.com/zachjs/sv2v.git
50 lines
1.5 KiB
Haskell
50 lines
1.5 KiB
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for unbased, unsized literals ('0, '1, 'z, 'x)
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-
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- The literals are given a binary base, a size of 1, and are made signed to
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- allow sign extension. This enables the desired implicit casting in
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- Verilog-2005.
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-
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- However, in a ternary expressions, these literals should take on the sign and
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- size of their counterpart. To work around this, we explicitly size cast these
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- literlas when they appear within a ternary expression.
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-}
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module Convert.UnbasedUnsized (convert) where
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: [AST] -> [AST]
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convert =
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map $
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traverseDescriptions $ traverseModuleItems $
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traverseExprs $ traverseNestedExprs convertExpr
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digits :: [Char]
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digits = ['0', '1', 'x', 'z', 'X', 'Z']
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literalFor :: Char -> Expr
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literalFor ch =
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if elem ch digits
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then Number ("1'sb" ++ [ch])
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else error $ "unexpected unbased-unsized digit: " ++ [ch]
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convertExpr :: Expr -> Expr
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convertExpr (Mux cond left right) =
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Mux cond (convertExprCast left right) (convertExprCast right left)
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convertExpr (Number ['\'', ch]) =
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literalFor ch
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convertExpr other = other
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convertExprCast :: Expr -> Expr -> Expr
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convertExprCast (Number ['\'', ch]) other =
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Cast (Right size) (literalFor ch)
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where
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size = case other of
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Number ['\'', _] -> Number "32"
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_ -> DimsFn FnBits $ Right other
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convertExprCast other _ = other
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